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Why Ciena:
You will be a member of a successful team working at forefront of technological innovation focused on innovative technologies, flows and products. You will be working with, and learning from industry-recognized experts.
Our team supports aninclusive, diverse and barrier-free work environment making for empowered and committed employees.
We recognize the importance of well-being and offer programs and benefits to support and sustain the mental and physical health of our employees and their families.
Great work deserves recognition. We have a robust recognition program, with ongoing and enhanced awards for exemplary performance.
Reporting to Sr. Manager ASIC Engineering, as a Senior ASIC/FPGA Engineer, you will:
Assist in the development of FPGA emulation platforms for Ciena's ASIC designs.
Develop HDL code for FPGAs.
Synthesize and simulate FPGA digital logic using industry-standard tools.
Find the technical root cause and suggest corrective action for given problems.
Write diagnostic firmware to validate FPGA designs.
The Must Haves:
Bachelor / Master or PhD degree in Electrical Engineering coupled with proven experience in ASIC/FPGA development with Verilog.
Minimum 5 years of work experience is required in ASIC/FPGA design.
Experience with ASIC/FPGA design, verification, synthesis, timing/power analysis and DFT.
Excellent communication skills.
Strong hands-on debug skills and lab experience.
Proficient with a programming language like C/C++.
Assets:
Knowledge of high-performance and low-power design techniques.
Knowledge of FPGA and emulation platforms. Knowledge of SOC architecture.
Experience with modern SoC design architectures, ARM/MiPs type processor cores, Ethernet, Networking, and Data Communications.
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